1. Field of the Invention
The present invention relates to a manufacturing process of a stacked semiconductor device and corresponding device.
More specifically, the invention relates to a manufacturing process of a stacked semiconductor device.
The invention also relates to a stacked semiconductor device comprising a first die mounted on a support.
The invention relates particularly, but not exclusively, to a manufacturing method of a stacked semiconductor device in so-called 3D packages for memory applications comprising a first die mounted on a support, an intermediate adhesive layer, a second die mounted on said adhesive layer, an intermediate layer, a third die and so on up to reaching a number of dies complying with the functions required by the final device and the following description is made with reference to this field of application for convenience of illustration only.
2. Description of the Related Art
As it is well known, the manufacture of a stacked semiconductor device in memory applications requires the integration of the ones on the other different semiconductor material dies, an electronic circuit being monolithically integrated on each die. In some of these applications dies have the same size. When this condition occurs it is necessary to introduce particular assembly methods to allow the different dies to be electrically connected with the support they are mounted on.
A first known solution to manufacture such devices is shown in FIG. 1.
A first die (called Mother die) 2 is mounted on a semiconductor substrate 1 through a traditional die attach process.
Electric connections are provided by means of the wire bonding technology between the die and the support in order to output electric signals. In order to keep the profile of the wires used for electric connections low and gain some thickness a reverse bonding technology is generally used. A glue layer 3, generally of the same type used to mount the first die on the support 1, is further deposited on this first die 2, whereon a second bearing die 4, called dummy die or interposer, being generally silicon-made, is rested and glue-fastened.
A further glue layer 5 is deposited on this second dummy die 4, whereon a third die or daughter die 6 is mounted.
Electric connections are provided by means of the wire bonding technology between the daughter die 6 and the substrate 1, by means of a reverse bonding technique. This process is reiterated as many times as the number of dies to be integrated. At present three dies are overlapped, but the number (in accordance with the die thickness) can even reach 8.
Although advantageous under several aspects, this first solution has several drawbacks. The first drawback is linked to the need to use a certain number of dummy dies 4 which are particularly expensive. These dummy dies 4 are assembled by die attack. The amount of glue being used and the manufacturing time increase accordingly. Moreover, to let the two dies be sufficiently spaced out it is necessary to use thick dummy dies. Consequently, very thin functional dies 2 and 6 are to be used. The reduction of the thickness of the functional die 2 and 6 beyond a certain value involves some criticalities and difficulties in the whole assembly process.
Moreover, the formation of several overlapped layers realized on a semiconductor substrate, which has already been split from the initial silicon wafer, poses different problems for the alignment and thus the reliability of the final device.
Another technology used to assemble stacked semiconductor devices is the use of glues containing spacers (glass fillers) which, although removing dummy dies 4, has the disadvantage of breaking the die protective layer called passivation layer.